Key Takeaways
- Different EDA suites generate wildly different file extensions for identical physical layers (.GTL in Altium vs. -F_Cu.gbr in KiCad vs. .cmp in Eagle).
- Confusing solder mask layers with copper layers or pasting mask layers can lead to catastrophic manufacturing errors such as fully unmasked or inverted circuit boards.
- Always include a dedicated board outline layer (.GKO, .GM1, or -Edge_Cuts.gbr) with clean, continuous zero-width perimeter lines.
- Inspecting all generated files in a standalone, client-side Gerber viewer before submitting fabrication orders prevents expensive CAM holds and production scrap.
1. The Tower of Babel in EDA Output Formats
One of the most persistent sources of confusion for junior electrical engineers and PCB hobbyists is the bewildering variety of file extensions found in Gerber archives. Why does Altium Designer generate .GTL, while KiCad generates -F_Cu.gbr, and Autodesk Eagle produces .cmp?
The explanation is rooted in EDA software history. The official RS-274X specification defined the syntax of the commands inside the file, but deliberately did not standardize the file extension. As a result, each EDA software vendor developed its own proprietary naming convention:
• Protel / Altium Convention: Originated the 3-letter extension standard based on physical layer mnemonics: G (Gerber), T/B (Top/Bottom), and L/S/O (Layer/Solder mask/Overlay). For example, .GTL stands for Gerber Top Layer, and .GBS stands for Gerber Bottom Solder mask.
• KiCad Descriptive Convention: Uses human-readable suffix tags appended to the project name, followed by a generic .gbr extension (e.g., project-F_Cu.gbr for Front Copper, project-B_Mask.gbr for Back Solder Mask).
• Eagle Legacy Convention: Uses Unix-style abbreviations derived from early German CAM tooling: .cmp (Component side), .sol (Solder side), .stc (Stop top component), and .pls (Placement silkscreen).
2. Cross-EDA Layer Extension Reference Matrix
To prevent ambiguity when exporting manufacturing packages or reviewing customer files, reference this definitive cross-EDA layer mapping matrix covering all major CAD suites:
| Layer Function | Altium Designer | KiCad (v7/v8) | Autodesk Eagle | Cadence Allegro |
|---|---|---|---|---|
| Top Copper | .GTL | -F_Cu.gbr | .cmp | top.art |
| Bottom Copper | .GBL | -B_Cu.gbr | .sol | bottom.art |
| Inner Copper 1 | .G1 / .GL2 | -In1_Cu.gbr | .ly2 | inner1.art |
| Inner Copper 2 | .G2 / .GL3 | -In2_Cu.gbr | .ly3 | inner2.art |
| Top Solder Mask | .GTS | -F_Mask.gbr | .stc | soldmask_top.art |
| Bottom Solder Mask | .GBS | -B_Mask.gbr | .sts | soldmask_bottom.art |
| Top Silkscreen | .GTO | -F_Silkscreen.gbr | .plc | silkscreen_top.art |
| Bottom Silkscreen | .GBO | -B_Silkscreen.gbr | .pls | silkscreen_bottom.art |
| Top Solder Paste | .GTP | -F_Paste.gbr | .crc | pastemask_top.art |
| Bottom Solder Paste | .GBP | -B_Paste.gbr | .crs | pastemask_bottom.art |
| Board Outline | .GKO / .GM1 | -Edge_Cuts.gbr | .gko / .dim | outline.art |
| NC Drill (Plated) | .DRL / .TXT | -PTH.drl | .drd / .txt | drill.art |
| NC Drill (Non-Plated) | .DRL / .TXT | -NPTH.drl | .drd / .txt | nptdrill.art |
3. Catastrophic Risks of Extension Mismatches
Mismatched or unrecognized file extensions are the number one cause of pre-production engineering holds (CAM holds) and, worse, fabricated scrap boards. Here are three common real-world failure modes caused by extension confusion:
1. Solder Mask vs. Paste Mask Confusion: Solder mask (.GTS/-F_Mask.gbr) defines where the protective epoxy coat is removed. Paste mask (.GTP/-F_Paste.gbr) defines laser openings for the stainless steel solder paste stencil. If a designer accidentally maps the paste mask file as the solder mask layer, the factory will expose solder mask only on component pads and coat the entire rest of the board with raw copper, rendering the PCB completely unusable.
2. Missing or Split Board Outline: High-volume fabricators use CNC routing bits guided by the board outline layer. In Altium, designers sometimes draw outlines on Mechanical 1 (.GM1) instead of the dedicated Keep-Out (.GKO). In KiCad, if the Edge.Cuts layer is missing from the ZIP, the automated CAM tool cannot detect the board dimensions and rejects the order.
3. Plated vs. Non-Plated Hole Merging: When mounting holes (NPTH) for chassis screws are merged into the main plated drill file without distinct tool headers, the factory will electroplate the hole barrel. This can cause severe electrical shorts to ground if metallic standoffs make contact with internal power planes.
If ordering from Asian rapid-turn manufacturers (such as JLCPCB), navigate to KiCad's Plot Dialog and check 'Use Protel filename extensions'. This automatically converts -F_Cu.gbr to .GTL and -Edge_Cuts.gbr to .GM1, ensuring 100% automated ingestion without manual review delays.
4. Standardized ZIP Archive Packaging Protocol
To guarantee seamless, touchless CAM processing, follow this clean archive packaging protocol before dispatching your PCB order:
• Single Top-Level Archive: Package all layer files and drill files directly in the root of the ZIP file. Do not nest them inside subdirectories.
• Unified Project Basename: Ensure all files share an identical project prefix (e.g., my_board_v1.0.GTL, my_board_v1.0.GBL, my_board_v1.0.TXT).
• Include Fabrication Notes: If your design requires specific impedance control (e.g., 50-ohm single-ended, 90-ohm USB differential) or non-standard copper thickness (2oz / 70µm), include a clear plain-text README.txt file inside the archive.
• Pre-Flight In-Browser Inspection: Before uploading, drag your completed ZIP archive into GerberPatch to verify that all layers superimpose with zero offset or scaling discrepancies.
Inspect your Gerber files 100% privately
Verify clearances, layers, and drill holes with zero cloud uploads in GerberPatch.